Abstract
We present a functional partitioning method for low power real-time embedded systems. The goal is to partition the system-level specification of a set of task graphs to realise a distributed system whose constituent nodes are systems-on-a-chip (SOCs). The proposed technique merges partitioning and system synthesis into one integrated process, implemented within a genetic algorithm. This technique satisfies both the hard real-time constraints and each SOC area constraint, and performs multi-objective optimisation, with multiple distributed system architectures produced that trade off overall system price and power consumption. Experimental results show the efficacy of the technique.
Original language | English (US) |
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Pages (from-to) | 2-13 |
Number of pages | 12 |
Journal | International Journal of Embedded Systems |
Volume | 1 |
Issue number | 1-2 |
DOIs | |
State | Published - 2005 |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
Keywords
- SOC synthesis
- distributed systems
- functional partitioning
- genetic algorithms
- hardware-software cosynthesis
- real-time embedded systems