Instruction set design and optimizations for address computation in DSP architectures

Guido Araujo, Ashok Sudarsanam, Sharad Malik

Research output: Contribution to journalConference articlepeer-review

34 Scopus citations


In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instruction design which can guarantee minimum overhead for programs that make use of implicit indirect addressing. Second, we give a formulation and propose a solution for the problem of allocating address registers (ARs) for array accesses within loop constructs. Third, we describe retargettable approaches for auto-increment (decrement) optimizations of pointer variables, and loop induction variables. Finally, we use a graph coloring technique to allocate physical ARs to the virtual ARs used in the previous phases. The results show that the combination of the above techniques considerably improves the final code quality for benchmark DSP programs.

Original languageEnglish (US)
Pages (from-to)102-107
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
StatePublished - 1996
EventProceedings of the 1996 9th International Symposium on System Synthesis, ISSS'96 - La Jolla, CA, USA
Duration: Nov 6 1996Nov 8 1996

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


Dive into the research topics of 'Instruction set design and optimizations for address computation in DSP architectures'. Together they form a unique fingerprint.

Cite this