TY - GEN
T1 - Input space adaptive embedded software synthesis
AU - Wang, Weidong
AU - Raghunathan, A.
AU - Lakshminarayana, G.
AU - Jha, N. K.
N1 - Funding Information:
This work was supported by DARPA under contract no. DAAB07-00-C-L516.
Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is based on the fact that the computational complexities of programs or sub-programs are often highly dependent on the values assumed by input and intermediate program variables during execution. This observation is exploited in the proposed software synthesis technique by augmenting the program with optimized versions of one or more sub-programs that are specialized to, and executed under, specific input sub-spaces. We propose a methodology for input space adaptive software synthesis which consists of the following steps: control and value profiling of the input program, application of compiler transformations as a preprocessing step, identification of sub-programs and corresponding input sub-spaces that hold the highest potential for optimization, and transformation of the sub-programs to realize performance and energy savings. We have evaluated input space adaptive software synthesis by compiling the resulting optimized programs to two commercial embedded processors (Fujitsu SPARClite™ and Intel StrongARM™). Our experiments indicate that our techniques can reduce energy consumption of the whole program by up to 7.8X (an average of 3.1X for SPARClite and 2.6X for StrongARM) while simultaneously improving performance by up to 8.5X (an average of 3.1X for SPARClite and 2.7X for StrongARM), leading to an improvement in the energy-delay product by up to 66.7X (an average of 8.2X for SPARClite and 6.3X for StrongARM), at the cost of minimal code size overheads (an average of 5.9%).
AB - This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is based on the fact that the computational complexities of programs or sub-programs are often highly dependent on the values assumed by input and intermediate program variables during execution. This observation is exploited in the proposed software synthesis technique by augmenting the program with optimized versions of one or more sub-programs that are specialized to, and executed under, specific input sub-spaces. We propose a methodology for input space adaptive software synthesis which consists of the following steps: control and value profiling of the input program, application of compiler transformations as a preprocessing step, identification of sub-programs and corresponding input sub-spaces that hold the highest potential for optimization, and transformation of the sub-programs to realize performance and energy savings. We have evaluated input space adaptive software synthesis by compiling the resulting optimized programs to two commercial embedded processors (Fujitsu SPARClite™ and Intel StrongARM™). Our experiments indicate that our techniques can reduce energy consumption of the whole program by up to 7.8X (an average of 3.1X for SPARClite and 2.6X for StrongARM) while simultaneously improving performance by up to 8.5X (an average of 3.1X for SPARClite and 2.7X for StrongARM), leading to an improvement in the energy-delay product by up to 66.7X (an average of 8.2X for SPARClite and 6.3X for StrongARM), at the cost of minimal code size overheads (an average of 5.9%).
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U2 - 10.1109/ASPDAC.2002.995018
DO - 10.1109/ASPDAC.2002.995018
M3 - Conference contribution
AN - SCOPUS:84962315066
T3 - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
SP - 711
EP - 718
BT - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Y2 - 7 January 2002 through 11 January 2002
ER -