Informing memory operations: providing memory performance feedback in modern processors

Mark Horowitz, Margaret Rose Martonosi, Todd C. Mowry, Michael D. Smith

Research output: Contribution to journalConference articlepeer-review

44 Scopus citations


A new class of memory operations called informing memory operations is proposed, which essentially consist of a memory operation combined either implicitly or explicitly with a conditional branch-and-link operation that is taken only if the reference suffers a cache miss. Two different implementations of informing memory operations are described, one based on cache-outcome condition code and another based on low-overhead traps; it is found that modern in-order-issue and out-of-order issue superscalar processors already contain the bulk of the necessary hardware support. This paper describes how a number of software-based memory optimizations can exploit informing memory operations to enhance performance, and takes a look at cache coherence with fine-grained access control as a case study.

Original languageEnglish (US)
Pages (from-to)260-270
Number of pages11
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - 1996
EventProceedings of the 1996 23rd Annual International Symposium on Computer Architecture - Philadelphia, PA, USA
Duration: May 22 1996May 24 1996

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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