In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects

Niket Agarwal, Li Shiuan Peh, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Scopus citations


Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networks would be needed in many-core chip multiprocessors (CMPs) to provide scalable on-chip communication. However, providing ordering among coherence transactions on unordered interconnects is a challenge. Traditional approaches for tackling coherence either have to use ordered interconnects (snoopbased protocols) which lead to scalability problems, or rely on an ordering point (directory-based protocols) which adds indirection latency. In this paper, we propose In-Network Snoop Ordering (INSO), in which coherence requests from a snoop-based protocolare inserted into the interconnect fabric and the network orders the requests in a distributed manner, creating a global ordering among requests. Essentially, when coherence requests enter the network, they grab snoop-orders at the injection router before being broadcasted. A snoop-order specifies the global ordering of the particular request with respect to other requests. Before requests reach their destinations, they get ordered along the way, at intermediate routers and destination network interfaces. Our logical ordering scheme can be mapped onto any unordered interconnect. This enables a cache coherence protocol which exploits the low-latency nature of unordered interconnects without adding indirection to coherence transactions. Our full-system evaluations compare INSO against a directory protocol and a broadcast based Token Coherence protocol. INSO outperforms these protocols by up to 30% and 8.5%, respectively, on a wide range of scientific and emerging applications.

Original languageEnglish (US)
Title of host publicationProceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009
PublisherIEEE Computer Society
Number of pages12
ISBN (Print)9781424429325
StatePublished - 2009
EventIEEE 15th International Symposium on High Performance Computer Architecture, HPCA 2009 - Raleigh, United States
Duration: Feb 14 2009Feb 18 2009

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897


ConferenceIEEE 15th International Symposium on High Performance Computer Architecture, HPCA 2009
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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