TY - GEN
T1 - Improving the performance of automatic sequential test generation by targeting hard-to-test faults
AU - Lingappan, Loganathan
AU - Jha, Niraj K.
PY - 2006
Y1 - 2006
N2 - Automatic test pattern generation (ATPG) for sequential circuits usually involves search for a sequence of vectors to detect single stuck-at faults. The sequential search space is exponential in the memory elements and primary inputs. Existing sequential test generators are known to spend substantial amounts of run-time in searching for test sequences to detect hard-to-test faults. In this paper, we present a pre-process stage that precedes sequential test generation for each hard-to-test fault and prunes the sequential search space, which in turn reduces the test generation time for these faults. In this stage, the effects of different conditions imposed on the circuit for test generation are propagated as far as possible. This process requires only a single pass through the iterative array model of the given circuit. Using the pre-process stage along with a Boolean satisfiability (SAT) based sequential test generator, we show that the proposed approach is on an average 11.3X (maximum 25.2X) faster than an efficient gate-level sequential test generator for hard-to-test faults in ISCAS'89 benchmark circuits. The proposed pre-process stage is also applicable to sequential test generation at the register-transfer level (RTL) and improves the overall performance of an efficient sequential test generator at the RTL by 3.5X on average and a maximum of 4.6X for all faults.
AB - Automatic test pattern generation (ATPG) for sequential circuits usually involves search for a sequence of vectors to detect single stuck-at faults. The sequential search space is exponential in the memory elements and primary inputs. Existing sequential test generators are known to spend substantial amounts of run-time in searching for test sequences to detect hard-to-test faults. In this paper, we present a pre-process stage that precedes sequential test generation for each hard-to-test fault and prunes the sequential search space, which in turn reduces the test generation time for these faults. In this stage, the effects of different conditions imposed on the circuit for test generation are propagated as far as possible. This process requires only a single pass through the iterative array model of the given circuit. Using the pre-process stage along with a Boolean satisfiability (SAT) based sequential test generator, we show that the proposed approach is on an average 11.3X (maximum 25.2X) faster than an efficient gate-level sequential test generator for hard-to-test faults in ISCAS'89 benchmark circuits. The proposed pre-process stage is also applicable to sequential test generation at the register-transfer level (RTL) and improves the overall performance of an efficient sequential test generator at the RTL by 3.5X on average and a maximum of 4.6X for all faults.
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U2 - 10.1109/VLSID.2006.104
DO - 10.1109/VLSID.2006.104
M3 - Conference contribution
AN - SCOPUS:33748554046
SN - 0769525024
SN - 9780769525020
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 431
EP - 436
BT - Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
T2 - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Y2 - 3 January 2006 through 7 January 2006
ER -