Abstract
This paper presents a new parallel volume rendering algorithm and implementation, based on shear warp factorization, for shared address space multiprocessors. Starting from an existing parallel shear-warp renderer, we use increasingly detailed performance measurements on real machines and simulators to understand performance bottlenecks. This leads us to a new parallel implementation that substantially outperforms and out-scales the old one on a range of shared address space platforms, from bus-based centralized memory machine to hardware-coherent distributed memory machines to networks of computers connected by page-based shared virtual memory. The results demonstrate that real time volume rendering is promising on general purpose multiprocessors, and illustrate the utility of tool hierarchies in conjunction with algorithmic and application knowledge to understand memory system interactions and improve parallel algorithms.
Original language | English (US) |
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Pages | 252-263 |
Number of pages | 12 |
DOIs | |
State | Published - 1997 |
Event | Proceedings of the 1997 6th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming - Las Vegas, NV, USA Duration: Jun 18 1997 → Jun 21 1997 |
Other
Other | Proceedings of the 1997 6th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming |
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City | Las Vegas, NV, USA |
Period | 6/18/97 → 6/21/97 |
All Science Journal Classification (ASJC) codes
- Software