TY - GEN
T1 - Implications of hierarchical N-body methods for multiprocessor architecture
AU - Singh, Jaswinder Pal
PY - 1992
Y1 - 1992
N2 - Summary form only given. The key architectural implications of realistically scaling a representative member of this important class of applications is examined. Using scaling methods that reflect the concerns of an application scientist leads to different conclusions than does naive scaling in terms of data set size. In particular, it is shown that under the most realistic scaling model, both the communication to computation ratio and the amount of cache memory per processor required for effective performance increase with scaling. The effect of a shared address space versus message passing as the communication abstraction is also examined. It is shown that the lack of a shared address space substantially increases the programming complexity and performance overheads of a message-passing implementation.
AB - Summary form only given. The key architectural implications of realistically scaling a representative member of this important class of applications is examined. Using scaling methods that reflect the concerns of an application scientist leads to different conclusions than does naive scaling in terms of data set size. In particular, it is shown that under the most realistic scaling model, both the communication to computation ratio and the amount of cache memory per processor required for effective performance increase with scaling. The effect of a shared address space versus message passing as the communication abstraction is also examined. It is shown that the lack of a shared address space substantially increases the programming complexity and performance overheads of a message-passing implementation.
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U2 - 10.1145/146628.140653
DO - 10.1145/146628.140653
M3 - Conference contribution
AN - SCOPUS:0026869163
SN - 0897915097
SN - 9780897915090
T3 - Conference Proceedings - Annual Symposium on Computer Architecture
SP - 436
BT - Conference Proceedings - Annual Symposium on Computer Architecture
PB - Publ by IEEE
T2 - 19th International Symposium on Computer Architecture
Y2 - 19 May 1992 through 21 May 1992
ER -