Implementing dynamic programming algorithms for signal and image processing on array processors

W. H. Chou; K. I. Diamantaras; S. Y. Kung

doi:10.1109/VLSISP.1993.404477

Implementing dynamic programming algorithms for signal and image processing on array processors

W. H. Chou, K. I. Diamantaras, S. Y. Kung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.

Original language	English (US)
Title of host publication	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	289-297
Number of pages	9
ISBN (Electronic)	0780309960, 9780780309968
DOIs	https://doi.org/10.1109/VLSISP.1993.404477
State	Published - 1993
Event	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands Duration: Oct 20 1993 → Oct 22 1993

Publication series

Name	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
Country/Territory	Netherlands
City	Veldhoven
Period	10/20/93 → 10/22/93

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Signal Processing
Software

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10.1109/VLSISP.1993.404477

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Chou, W. H., Diamantaras, K. I., & Kung, S. Y. (1993). Implementing dynamic programming algorithms for signal and image processing on array processors. In Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 (pp. 289-297). Article 404477 (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1993.404477

@inproceedings{ac69cb6ff24e4bf086d8b8f0df5431ae,

title = "Implementing dynamic programming algorithms for signal and image processing on array processors",

abstract = "The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.",

author = "Chou, {W. H.} and Diamantaras, {K. I.} and Kung, {S. Y.}",

note = "Publisher Copyright: {\textcopyright} 1993 IEEE.; 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 ; Conference date: 20-10-1993 Through 22-10-1993",

year = "1993",

doi = "10.1109/VLSISP.1993.404477",

language = "English (US)",

series = "Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "289--297",

booktitle = "Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993",

address = "United States",

}

Chou, WH, Diamantaras, KI & Kung, SY 1993, Implementing dynamic programming algorithms for signal and image processing on array processors. in Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993., 404477, Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993, Institute of Electrical and Electronics Engineers Inc., pp. 289-297, 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993, Veldhoven, Netherlands, 10/20/93. https://doi.org/10.1109/VLSISP.1993.404477

Implementing dynamic programming algorithms for signal and image processing on array processors. / Chou, W. H.; Diamantaras, K. I.; Kung, S. Y.
Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993. Institute of Electrical and Electronics Engineers Inc., 1993. p. 289-297 404477 (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Implementing dynamic programming algorithms for signal and image processing on array processors

AU - Chou, W. H.

AU - Diamantaras, K. I.

AU - Kung, S. Y.

PY - 1993

Y1 - 1993

N2 - The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.

AB - The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.

UR - http://www.scopus.com/inward/record.url?scp=85013484546&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85013484546&partnerID=8YFLogxK

U2 - 10.1109/VLSISP.1993.404477

DO - 10.1109/VLSISP.1993.404477

M3 - Conference contribution

AN - SCOPUS:85013484546

T3 - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

SP - 289

EP - 297

BT - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993

Y2 - 20 October 1993 through 22 October 1993

ER -

Chou WH, Diamantaras KI, Kung SY. Implementing dynamic programming algorithms for signal and image processing on array processors. In Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993. Institute of Electrical and Electronics Engineers Inc. 1993. p. 289-297. 404477. (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993). doi: 10.1109/VLSISP.1993.404477

Implementing dynamic programming algorithms for signal and image processing on array processors

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