Implementing dynamic programming algorithms for signal and image processing on array processors

W. H. Chou, K. I. Diamantaras, S. Y. Kung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages289-297
Number of pages9
ISBN (Electronic)0780309960, 9780780309968
DOIs
StatePublished - Jan 1 1993
Event6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands
Duration: Oct 20 1993Oct 22 1993

Publication series

NameProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Conference

Conference6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
Country/TerritoryNetherlands
CityVeldhoven
Period10/20/9310/22/93

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Signal Processing
  • Software

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