TY - GEN
T1 - Implementing dynamic programming algorithms for signal and image processing on array processors
AU - Chou, W. H.
AU - Diamantaras, K. I.
AU - Kung, S. Y.
PY - 1993/1/1
Y1 - 1993/1/1
N2 - The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.
AB - The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.
UR - http://www.scopus.com/inward/record.url?scp=85013484546&partnerID=8YFLogxK
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U2 - 10.1109/VLSISP.1993.404477
DO - 10.1109/VLSISP.1993.404477
M3 - Conference contribution
AN - SCOPUS:85013484546
T3 - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
SP - 289
EP - 297
BT - Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
Y2 - 20 October 1993 through 22 October 1993
ER -