This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.
|Original language||English (US)|
|Number of pages||1|
|Journal||IEEE Computer Architecture Letters|
|State||Published - 2002|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture