Implementing decay techniques using 4t quasi-static memory cells

Philo Juangt; Zhigang Hu; Margaret Rose Martonosi; Douglas Clark

doi:10.1109/L-CA.2002.5

Implementing decay techniques using 4t quasi-static memory cells

Philo Juangt, Zhigang Hu, Margaret Rose Martonosi, Douglas Clark

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.

Original language	English (US)
Pages (from-to)	10
Number of pages	1
Journal	IEEE Computer Architecture Letters
Volume	1
Issue number	1
DOIs	https://doi.org/10.1109/L-CA.2002.5
State	Published - 2002

All Science Journal Classification (ASJC) codes

Hardware and Architecture

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10.1109/L-CA.2002.5

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title = "Implementing decay techniques using 4t quasi-static memory cells",

abstract = "This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.",

author = "Philo Juangt and Zhigang Hu and Martonosi, {Margaret Rose} and Douglas Clark",

note = "Funding Information: This material is based upon work supported in part by the National Science Foundation under grants CCR-0082671, CCR-0086031, and CCR-0105626. In addition, the authors gratefully acknowledge the support of the University of Virginia Fund for Excellence in Science and Technology, Intel, IBM, and Agere Systems.",

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AU - Juangt, Philo

AU - Hu, Zhigang

AU - Martonosi, Margaret Rose

AU - Clark, Douglas

N1 - Funding Information: This material is based upon work supported in part by the National Science Foundation under grants CCR-0082671, CCR-0086031, and CCR-0105626. In addition, the authors gratefully acknowledge the support of the University of Virginia Fund for Excellence in Science and Technology, Intel, IBM, and Agere Systems.

PY - 2002

Y1 - 2002

N2 - This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.

AB - This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.

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JO - IEEE Computer Architecture Letters

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Implementing decay techniques using 4t quasi-static memory cells

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