Implementing decay techniques using 4t quasi-static memory cells

Philo Juangt, Zhigang Hu, Margaret Rose Martonosi, Douglas Clark

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.

Original languageEnglish (US)
Number of pages1
JournalIEEE Computer Architecture Letters
Volume1
Issue number1
DOIs
StatePublished - Jan 1 2002

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Implementing decay techniques using 4t quasi-static memory cells'. Together they form a unique fingerprint.

  • Cite this