TY - GEN
T1 - Impact of configurability and extensibility on IPSec protocol execution on embedded processors
AU - Potlapally, Nachiketh R.
AU - Ravi, Srivaths
AU - Raghunalhan, Anand
AU - Lee, Ruby B.
AU - Jha, Niraj K.
PY - 2006
Y1 - 2006
N2 - Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, in particular, the modest capabilities of embedded processors make it challenging to achieve satisfactory performance while executing security protocols. A promising approach for improving performance in embedded systems is to use application-specific instruction set processors that an. designed based on configurable and. extensible processors. In this work, we perform a comprehensive performance analysis of the IPSec protocol on a state-of-the-art configurable and extensible embedded processor (Xtensa from Tensilica, Inc.). We present performance profiles of a lightweight embedded IPSec implementation running on the Xtensa processor, and examine in detail the various factors that contribute to the processing latencies, including cryptographic and protocol processing. In order to improve the efficiency of IPSec processing on embedded devices, we then study the impact of customizing an embedded processor by synergistically (a) configuring architectural parameters, such as instruction and data cache sizes, processor-memory interface width, write buffers, etc., and (b) extending the base instruction set of the processor using custom instructions for both cryptographic and protocol processing. Our experimental results demonstrate that upto 6X speedup in IPSec processing is possible over a popular embedded IPSec software implementation.
AB - Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, in particular, the modest capabilities of embedded processors make it challenging to achieve satisfactory performance while executing security protocols. A promising approach for improving performance in embedded systems is to use application-specific instruction set processors that an. designed based on configurable and. extensible processors. In this work, we perform a comprehensive performance analysis of the IPSec protocol on a state-of-the-art configurable and extensible embedded processor (Xtensa from Tensilica, Inc.). We present performance profiles of a lightweight embedded IPSec implementation running on the Xtensa processor, and examine in detail the various factors that contribute to the processing latencies, including cryptographic and protocol processing. In order to improve the efficiency of IPSec processing on embedded devices, we then study the impact of customizing an embedded processor by synergistically (a) configuring architectural parameters, such as instruction and data cache sizes, processor-memory interface width, write buffers, etc., and (b) extending the base instruction set of the processor using custom instructions for both cryptographic and protocol processing. Our experimental results demonstrate that upto 6X speedup in IPSec processing is possible over a popular embedded IPSec software implementation.
KW - Configurability
KW - Embedded Processors
KW - Embedded Security
KW - Embedded Systems
KW - Extensibility
KW - IPSec
KW - Performance
KW - Security Protocols
UR - http://www.scopus.com/inward/record.url?scp=33748546240&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748546240&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2006.102
DO - 10.1109/VLSID.2006.102
M3 - Conference contribution
AN - SCOPUS:33748546240
SN - 0769525024
SN - 9780769525020
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 299
EP - 304
BT - Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
T2 - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Y2 - 3 January 2006 through 7 January 2006
ER -