IMPACT: A high-level synthesis system for low power control-flow intensive circuits

Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha

Research output: Contribution to journalConference article

10 Scopus citations

Abstract

In this paper, we present a comprehensive high-level synthesis system that is geared towards reducing power consumption in control-flow intensive circuits. An iterative improvement algorithm is at the heart of the system. The algorithm searches the design space by handling scheduling, module selection, resource sharing and multiplexer network restructuring simultaneously. The scheduler performs concurrent loop optimization and implicit loop unrolling. It minimizes the expected number of cycles of the schedule without compromising on the minimum and maximum schedule lengths. A fast simulation technique based on trace manipulation aids power estimation in driving synthesis in the right direction. Experimental results demonstrate power reduction of up to 85% with minimal overhead in area over area-optimized designs operating at 5 V.

Original languageEnglish (US)
Article number655957
Pages (from-to)848-854
Number of pages7
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - Dec 1 1998
EventDesign, Automation and Test in Europe, DATE 1998 - Paris, France
Duration: Feb 23 1998Feb 26 1998

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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