In this paper, we present a comprehensive high-level synthesis system that is geared towards reducing power consumption in control-flow intensive circuits. An iterative improvement algorithm is at the heart of the system. The algorithm searches the design space by handling scheduling, module selection, resource sharing and multiplexer network restructuring simultaneously. The scheduler performs concurrent loop optimization and implicit loop unrolling. It minimizes the expected number of cycles of the schedule without compromising on the minimum and maximum schedule lengths. A fast simulation technique based on trace manipulation aids power estimation in driving synthesis in the right direction. Experimental results demonstrate power reduction of up to 85% with minimal overhead in area over area-optimized designs operating at 5 V.
|Original language||English (US)|
|Number of pages||7|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 1998|
|Event||Design, Automation and Test in Europe, DATE 1998 - Paris, France|
Duration: Feb 23 1998 → Feb 26 1998
All Science Journal Classification (ASJC) codes