Abstract
We consider an image processing pipeline that enables a user to capture and generate high quality images from a digital camera. In such a system, some image processing tasks are typically implemented within the camera, while others are performed in software on a host computer that controls the output device. We consider the complexity issues and tradeoffs involved in designing several key algorithms in such a system. We also discuss hardware features that accelerate these algorithms.
Original language | English (US) |
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Pages | 280-285 |
Number of pages | 6 |
State | Published - 1997 |
Event | Proceedings of the 1997 IEEE COMPCON Conference - San Jose, CA, USA Duration: Feb 23 1997 → Feb 26 1997 |
Other
Other | Proceedings of the 1997 IEEE COMPCON Conference |
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City | San Jose, CA, USA |
Period | 2/23/97 → 2/26/97 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture