Abstract
While software is already a significant component in today's system-on-silicon, it is expected to greatly dominate future generations of systems-on-silicon that will contain several (possibly heterogeneous) programmable processors, as well as reconfigurable hardware blocks and large amounts of on-chip memory. In this context, one could argue that the problems for compiler designers haven't changed at all, since the basic issues all boil down to the traditional challenges of 1) coarse-grain parallelism extraction for the multiple processors on chip, 2) instruction-level parallelism exploitation for individual processors, and 3) retargetable code generation for versions of the on-chip processors. This paper summarizes the positions of the panelists who presented their views on the new challenges in compilers for future systems-on-silicon, and who debated these issues at ICCD'97.
| Original language | English (US) |
|---|---|
| Pages | 322-325 |
| Number of pages | 4 |
| State | Published - 1997 |
| Externally published | Yes |
| Event | Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA Duration: Oct 12 1997 → Oct 15 1997 |
Other
| Other | Proceedings of the 1997 International Conference on Computer Design |
|---|---|
| City | Austin, TX, USA |
| Period | 10/12/97 → 10/15/97 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering