Hybrid large-area systems and their interconnection backbone (invited paper)

Naveen Verma; L. Aygun; Y. Afsar; Y. Hu; L. Huang; T. Moy; J. Sanz-Robinson; W. Rieutort-Louis; S. Wagner; J. C. Sturm

doi:10.1109/NOCS.2016.7579342

Hybrid large-area systems and their interconnection backbone (invited paper)

Naveen Verma, L. Aygun, Y. Afsar, Y. Hu, L. Huang, T. Moy, J. Sanz-Robinson, W. Rieutort-Louis, S. Wagner, J. C. Sturm

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.

Original language	English (US)
Title of host publication	2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467390309
DOIs	https://doi.org/10.1109/NOCS.2016.7579342
State	Published - Sep 28 2016
Event	10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016 - Nara, Japan Duration: Aug 31 2016 → Sep 2 2016

Publication series

Name	2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016

Other

Other	10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016
Country/Territory	Japan
City	Nara
Period	8/31/16 → 9/2/16

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Hardware and Architecture

Keywords

Large-area electronics
hybrid systems
thin-film transistors

Access to Document

10.1109/NOCS.2016.7579342

Cite this

Verma, N., Aygun, L., Afsar, Y., Hu, Y., Huang, L., Moy, T., Sanz-Robinson, J., Rieutort-Louis, W., Wagner, S., & Sturm, J. C. (2016). Hybrid large-area systems and their interconnection backbone (invited paper). In 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016 [7579342] (2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NOCS.2016.7579342

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abstract = "Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.",

keywords = "Large-area electronics, hybrid systems, thin-film transistors",

author = "Naveen Verma and L. Aygun and Y. Afsar and Y. Hu and L. Huang and T. Moy and J. Sanz-Robinson and W. Rieutort-Louis and S. Wagner and Sturm, {J. C.}",

note = "Funding Information: This work was supported by NSF (grants ECCS-1202168 and CCF-1218206) and Systems on Nanoscale Information fabriCs (SONIC), one of six SRC STARnet Centers, sponsored by MARCO and DARPA. Publisher Copyright: {\textcopyright} 2016 IEEE.; 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016 ; Conference date: 31-08-2016 Through 02-09-2016",

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doi = "10.1109/NOCS.2016.7579342",

language = "English (US)",

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Verma, N, Aygun, L, Afsar, Y, Hu, Y, Huang, L, Moy, T, Sanz-Robinson, J, Rieutort-Louis, W, Wagner, S & Sturm, JC 2016, Hybrid large-area systems and their interconnection backbone (invited paper). in 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016., 7579342, 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Institute of Electrical and Electronics Engineers Inc., 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, 8/31/16. https://doi.org/10.1109/NOCS.2016.7579342

Hybrid large-area systems and their interconnection backbone (invited paper). / Verma, Naveen; Aygun, L.; Afsar, Y. et al.

2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7579342 (2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Hybrid large-area systems and their interconnection backbone (invited paper)

AU - Verma, Naveen

AU - Aygun, L.

AU - Afsar, Y.

AU - Hu, Y.

AU - Huang, L.

AU - Moy, T.

AU - Sanz-Robinson, J.

AU - Rieutort-Louis, W.

AU - Wagner, S.

AU - Sturm, J. C.

N1 - Funding Information: This work was supported by NSF (grants ECCS-1202168 and CCF-1218206) and Systems on Nanoscale Information fabriCs (SONIC), one of six SRC STARnet Centers, sponsored by MARCO and DARPA. Publisher Copyright: © 2016 IEEE.

PY - 2016/9/28

Y1 - 2016/9/28

N2 - Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.

AB - Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.

KW - Large-area electronics

KW - hybrid systems

KW - thin-film transistors

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M3 - Conference contribution

AN - SCOPUS:84994666281

T3 - 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016

BT - 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016

Y2 - 31 August 2016 through 2 September 2016

ER -

Verma N, Aygun L, Afsar Y, Hu Y, Huang L, Moy T et al. Hybrid large-area systems and their interconnection backbone (invited paper). In 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7579342. (2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016). doi: 10.1109/NOCS.2016.7579342

Hybrid large-area systems and their interconnection backbone (invited paper)

Abstract

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All Science Journal Classification (ASJC) codes

Keywords

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