Hybrid large-area systems and their interconnection backbone (invited paper)

Naveen Verma, L. Aygun, Y. Afsar, Y. Hu, L. Huang, T. Moy, J. Sanz-Robinson, W. Rieutort-Louis, S. Wagner, J. C. Sturm

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.

Original languageEnglish (US)
Title of host publication2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467390309
DOIs
StatePublished - Sep 28 2016
Event10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016 - Nara, Japan
Duration: Aug 31 2016Sep 2 2016

Publication series

Name2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016

Other

Other10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016
CountryJapan
CityNara
Period8/31/169/2/16

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture

Keywords

  • Large-area electronics
  • hybrid systems
  • thin-film transistors

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