Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of co-processor generation and custom instruction addition for extensible processors. However, we argue that there is a need for hybrid synthesis techniques by demonstrating that a combination of custom instructions and co-processors is often the better solution in many applications. We propose a systematic methodology that builds on basic observations and trade-offs associated with co-processors and custom instructions: co-processors are good for performing coarse-grained tasks that require minimal intervention or support from the processor, while custom instructions are efficient solutions for fine-grained tasks that are best integrated into a processor's pipeline. We have developed a hierarchical synthesis How that incorporates a muti-objective evolutionary algorithm in order to handle diverse design dimensions such as area, performance. We have implemented the proposed methodology in the context of a commercial extensible processor based platform (Xtensa™ from Tensilica). Our design flow incorporates a commercial behavioral synthesis tool and an automatic custom instruction generation engine. Our experiments with several applications show that simultaneous custom instruction and co-processor synthesis can achieve significantly better area/performance trade-offs than using only one of them.

Original languageEnglish (US)
Title of host publicationProceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Pages473-476
Number of pages4
DOIs
StatePublished - Sep 18 2006
Event19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design - Hyderabad, India
Duration: Jan 3 2006Jan 7 2006

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2006
ISSN (Print)1063-9667

Other

Other19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
CountryIndia
CityHyderabad
Period1/3/061/7/06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Sun, F., Ravi, S., Raghunathan, A., & Jha, N. K. (2006). Hybrid custom instruction and co-processor synthesis methodology for extensible processors. In Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (pp. 473-476). [1581496] (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2006). https://doi.org/10.1109/VLSID.2006.100