Hybrid custom instruction and co-processor synthesis methodology for extensible processors

Classical hardware/software partitioning techniques, recent advances in application-specific instruction set architecture (ISA) design tools, etc., provide avenues to address the individual problems of co-processor generation and custom instruction addition for extensible processors. However, we argue that there is a need for hybrid synthesis techniques by demonstrating that a combination of custom instructions and co-processors is often the better solution in many applications. We propose a systematic methodology that builds on basic observations and trade-offs associated with co-processors and custom instructions: co-processors are good for performing coarse-grained tasks that require minimal intervention or support from the processor, while custom instructions are efficient solutions for fine-grained tasks that are best integrated into a processor's pipeline. We have developed a hierarchical synthesis How that incorporates a muti-objective evolutionary algorithm in order to handle diverse design dimensions such as area, performance. We have implemented the proposed methodology in the context of a commercial extensible processor based platform (Xtensa™ from Tensilica). Our design flow incorporates a commercial behavioral synthesis tool and an automatic custom instruction generation engine. Our experiments with several applications show that simultaneous custom instruction and co-processor synthesis can achieve significantly better area/performance trade-offs than using only one of them.