HP's PA7100LC: a low-cost superscalar PA-RISC processor

Patrick Knebel, Barry Arnold, Mick Bass, Wayne Kever, Joel D. Lamb, Ruby B. Lee, Paul L. Perez, Stephen Undy, Will Walker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


HP has designed a new low-cost, superscalar PA-RISC processor including two integer ALU's, floating-point coprocessor, and a memory and I/O controller on a single VLSI chip. It implements the full PA-RISC1.1 functionality and adds several new features, including little-endian capability, uncacheable memory pages, and new multimedia instructions. The chip is fabricated in 0.8 micron, 3-level metal CMOS and is designed to run from 0-75 MHz. The cache system consists of an off-chip combined instruction/data cache ranging from 8K to 2MBytes and a small on-chip instruction buffer. Memory consists of 4MB to 3GBytes of standard DRAM's or SIMM's connecting directly to the processor chip. The chip achieves performance levels comparable to previous generation high-end workstations while lowering overall system cost and power consumption to enable a new generation of low-cost systems.

Original languageEnglish (US)
Title of host publication1993 IEEE Compcon Spring
PublisherPubl by IEEE
Number of pages7
ISBN (Print)0780312945
StatePublished - 1993
Event38th Annual IEEE Computer Society International Computer Conference - COMPCON SPRING '93 - San Francisco, CA, USA
Duration: Feb 22 1993Feb 26 1993

Publication series

Name1993 IEEE Compcon Spring


Other38th Annual IEEE Computer Society International Computer Conference - COMPCON SPRING '93
CitySan Francisco, CA, USA

All Science Journal Classification (ASJC) codes

  • General Engineering


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