High temperature polycrystalline silicon thin film transistor on steel substrates

Ming Wu, Kiran Pangal, James C. Sturm, Sigurd Wagner

Research output: Contribution to journalConference article

9 Scopus citations

Abstract

Polycrystalline silicon thin film transistors were fabricated using both self-aligned and non-self-aligned structures on 0.2 mm steel foil substrates coated with 0.5 μm SiO2. The polycrystalline silicon was formed by furnace crystallization of PECVD hydrogenated amorphous silicon films at temperatures from 600 to 950°C. The corresponding annealing times at high temperature can be as short as 20 seconds. No evidence is found for transistor contamination by the steel with drain current on/off ratio of ≥105 in all cases. The short crystallization times achievable on steel substrates provide a considerable advantage over glass substrates, which require crystallization times of ≥6 hours because of their strain temperatures of approx.600°C. Our results lay the groundwork for polycrystalline silicon transistor roll-to-roll technology on continuous web.

Original languageEnglish (US)
Pages (from-to)119-122
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - Dec 1 1999
Event1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: Dec 5 1999Dec 8 1999

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Fingerprint Dive into the research topics of 'High temperature polycrystalline silicon thin film transistor on steel substrates'. Together they form a unique fingerprint.

  • Cite this