High-level test synthesis: A survey

Indradeep Ghosh, Niraj K. Jha

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


This paper surveys the various high-level design for testability and synthesis for testability methods that have been proposed in the last decade. We begin with a description of high-level synthesis methods which target the ease of subsequent gate-level sequential test generation. Then we describe high-level synthesis methods which target built-in self-test (BIST) and hierarchical testability. Thereafter, we describe register-transfer level testability techniques that target gate-level test generation, BIST and hierarchical testability. We then describe some high-level test generation methods in brief.

Original languageEnglish (US)
Pages (from-to)79-99
Number of pages21
JournalIntegration, the VLSI Journal
Issue number1-2
StatePublished - Dec 1 1998

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


  • Design for testability
  • Digital system testing
  • High-level synthesis
  • Register-transfer level synthesis
  • Synthesis for testability


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