TY - JOUR
T1 - High-level test compaction techniques
AU - Ravi, Srivaths
AU - Lakshminarayana, Ganesh
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received November 2, 2000; revised December 23, 2001. This work was supported in part by the National Science Foundation under Grant MIP-9729441 and in part by the New Jersey Commission on Science and Technology. This paper was recommended by Associate Editor S. Reddy. S. Ravi is with C & C Research Labs, NEC USA, Princeton, NJ 08540 USA. G. Lakshminarayana is with the Alphion Corp., Eatontown, NJ 07724 USA. N. K. Jha is with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA. Publisher Item Identifier S 0278-0070(02)05625-7.
PY - 2002/7
Y1 - 2002/7
N2 - Available register-transfer level (RTL) test generation techniques do not make a concerted effort to reduce the test application time associated with the derived tests. Chip tester memory limitations, increasing tester costs, etc., make it imperative that the issue of generating compact tests at the RTL be addressed and consolidated with the known gains of high-level testing. In this paper, the authors provide a comprehensive framework for generating compact tests for an RTL circuit. They develop a series of techniques that exploit the inherent parallelism available in symbolic test(s) derived for RTL module(s). These techniques enable them to schedule testing of multiple modules in parallel as well as perform test pipelining. In addition, the authors also present design for testability (DFT) techniques for lowering test application time. Using a maximum bipartite matching formulation, they choose a low-overhead set of test enhancements that can achieve compact tests. The authors' techniques can seamlessly plug into any generic high-level test framework. Their experimental results in the context of one such framework indicate that the proposed methodology achieves an average reduction in test application time of 54.2% for the example circuits.
AB - Available register-transfer level (RTL) test generation techniques do not make a concerted effort to reduce the test application time associated with the derived tests. Chip tester memory limitations, increasing tester costs, etc., make it imperative that the issue of generating compact tests at the RTL be addressed and consolidated with the known gains of high-level testing. In this paper, the authors provide a comprehensive framework for generating compact tests for an RTL circuit. They develop a series of techniques that exploit the inherent parallelism available in symbolic test(s) derived for RTL module(s). These techniques enable them to schedule testing of multiple modules in parallel as well as perform test pipelining. In addition, the authors also present design for testability (DFT) techniques for lowering test application time. Using a maximum bipartite matching formulation, they choose a low-overhead set of test enhancements that can achieve compact tests. The authors' techniques can seamlessly plug into any generic high-level test framework. Their experimental results in the context of one such framework indicate that the proposed methodology achieves an average reduction in test application time of 54.2% for the example circuits.
KW - Design for testability
KW - RTL test generation
KW - Symbolic testing
KW - Test compaction
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U2 - 10.1109/TCAD.2002.1013895
DO - 10.1109/TCAD.2002.1013895
M3 - Article
AN - SCOPUS:0036638287
SN - 0278-0070
VL - 21
SP - 827
EP - 841
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 7
ER -