High-level synthesis of multi-process behavioral descriptions

Weidong Wang, Anand Raghunathan, Niraj Kumar Jha, Sujit Dey

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.

Original languageEnglish (US)
Title of host publicationProceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
PublisherIEEE Computer Society
Pages467-473
Number of pages7
ISBN (Electronic)0769518680
DOIs
StatePublished - Jan 1 2003
Event16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India
Duration: Jan 4 2003Jan 8 2003

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2003-January
ISSN (Print)1063-9667

Other

Other16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
CountryIndia
CityNew Delhi
Period1/4/031/8/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Contracts
  • Digital circuits
  • Hardware design languages
  • High level synthesis
  • National electric code
  • Optimization methods
  • Partitioning algorithms
  • Performance analysis
  • Resource management
  • Timing

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  • Cite this

    Wang, W., Raghunathan, A., Jha, N. K., & Dey, S. (2003). High-level synthesis of multi-process behavioral descriptions. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design (pp. 467-473). [1183178] (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January). IEEE Computer Society. https://doi.org/10.1109/ICVD.2003.1183178