High-level synthesis of multi-process behavioral descriptions

Weidong Wang; Anand Raghunathan; Niraj K. Jha; Sujit Dey

doi:10.1109/ICVD.2003.1183178

High-level synthesis of multi-process behavioral descriptions

Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.

Original language	English (US)
Title of host publication	Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
Publisher	IEEE Computer Society
Pages	467-473
Number of pages	7
ISBN (Electronic)	0769518680
DOIs	https://doi.org/10.1109/ICVD.2003.1183178
State	Published - 2003
Event	16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India Duration: Jan 4 2003 → Jan 8 2003

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
Volume	2003-January
ISSN (Print)	1063-9667

Other

Other	16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
Country/Territory	India
City	New Delhi
Period	1/4/03 → 1/8/03

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Keywords

Contracts
Digital circuits
Hardware design languages
High level synthesis
National electric code
Optimization methods
Partitioning algorithms
Performance analysis
Resource management
Timing

Access to Document

10.1109/ICVD.2003.1183178

Cite this

Wang, W., Raghunathan, A., Jha, N. K., & Dey, S. (2003). High-level synthesis of multi-process behavioral descriptions. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design (pp. 467-473). Article 1183178 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January). IEEE Computer Society. https://doi.org/10.1109/ICVD.2003.1183178

Wang, Weidong ; Raghunathan, Anand ; Jha, Niraj K. et al. / High-level synthesis of multi-process behavioral descriptions. Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society, 2003. pp. 467-473 (Proceedings of the IEEE International Conference on VLSI Design).

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title = "High-level synthesis of multi-process behavioral descriptions",

abstract = "This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.",

keywords = "Contracts, Digital circuits, Hardware design languages, High level synthesis, National electric code, Optimization methods, Partitioning algorithms, Performance analysis, Resource management, Timing",

author = "Weidong Wang and Anand Raghunathan and Jha, {Niraj K.} and Sujit Dey",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design ; Conference date: 04-01-2003 Through 08-01-2003",

year = "2003",

doi = "10.1109/ICVD.2003.1183178",

language = "English (US)",

series = "Proceedings of the IEEE International Conference on VLSI Design",

publisher = "IEEE Computer Society",

pages = "467--473",

booktitle = "Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design",

address = "United States",

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Wang, W, Raghunathan, A, Jha, NK & Dey, S 2003, High-level synthesis of multi-process behavioral descriptions. in Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design., 1183178, Proceedings of the IEEE International Conference on VLSI Design, vol. 2003-January, IEEE Computer Society, pp. 467-473, 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design, New Delhi, India, 1/4/03. https://doi.org/10.1109/ICVD.2003.1183178

High-level synthesis of multi-process behavioral descriptions. / Wang, Weidong; Raghunathan, Anand; Jha, Niraj K. et al.
Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society, 2003. p. 467-473 1183178 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Raghunathan, Anand

AU - Jha, Niraj K.

AU - Dey, Sujit

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N2 - This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.

AB - This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.

KW - Contracts

KW - Digital circuits

KW - Hardware design languages

KW - High level synthesis

KW - National electric code

KW - Optimization methods

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KW - Timing

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BT - Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design

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Wang W, Raghunathan A, Jha NK, Dey S. High-level synthesis of multi-process behavioral descriptions. In Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design. IEEE Computer Society. 2003. p. 467-473. 1183178. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/ICVD.2003.1183178

High-level synthesis of multi-process behavioral descriptions

Abstract

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All Science Journal Classification (ASJC) codes

Keywords

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