TY - JOUR
T1 - High-level synthesis of low-power control-flow intensive circuits
AU - Khouri, Kamal S.
AU - Lakshminarayana, Ganesh
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received June 11, 1998; revised May 24, 1999. This work was supported in part by Alternative System Concepts under an SBIR contract from Air Force Rome Laboratories and in part by NSF under Grant MIP-9319269. This paper was recommended by Associate Editor R. Camposano. K. S. Khouri and N. K. Jha are with Princeton University, Princeton, NJ 08544 USA. G. Lakshminarayana is with NEC CCRL, Princeton, NJ 08544 USA. Publisher Item Identifier S 0278-0070(99)09916-9.
PY - 1999/12
Y1 - 1999/12
N2 - In this paper, we present a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection, and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process. Experimental results for a number of control-flow intensive and data-dominated benchmarks demonstrate power reduction of up to 62% (58%) when compared to Vdd-scaled area-optimized (delay-optimized) designs. The area overheads over area-optimized designs are less than 39%, whereas the area savings over delay-optimized designs are up to 40%.
AB - In this paper, we present a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection, and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process. Experimental results for a number of control-flow intensive and data-dominated benchmarks demonstrate power reduction of up to 62% (58%) when compared to Vdd-scaled area-optimized (delay-optimized) designs. The area overheads over area-optimized designs are less than 39%, whereas the area savings over delay-optimized designs are up to 40%.
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U2 - 10.1109/43.811321
DO - 10.1109/43.811321
M3 - Article
AN - SCOPUS:0033332247
SN - 0278-0070
VL - 18
SP - 1715
EP - 1729
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 12
ER -