High-level synthesis algorithms for power and temperature minimization

Li Shang, Robert P. Dick, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingChapter

6 Scopus citations

Abstract

Increasing digital system complexity and integration density motivate automation of the integrated circuit design process. High-level synthesis is a promising method of increasing designer productivity. Continued process scaling and increasing integration density result in increased power consumption, power density, and temperature. High-level synthesis for integrated circuit (IC) power and thermal optimization has been an active research area in the recent past. This chapter explains the challenges power and temperature optimization pose for high-level synthesis researchers and summarizes research progress to date.

Original languageEnglish (US)
Title of host publicationHigh-Level Synthesis
Subtitle of host publicationFrom Algorithm to Digital Circuit
PublisherSpringer Netherlands
Pages285-297
Number of pages13
ISBN (Print)9781402085871
DOIs
StatePublished - Dec 1 2008

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Keywords

  • Behavioral synthesis
  • High-level synthesis
  • Power
  • Reliability
  • Temperature
  • Thermal modeling

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    Shang, L., Dick, R. P., & Jha, N. K. (2008). High-level synthesis algorithms for power and temperature minimization. In High-Level Synthesis: From Algorithm to Digital Circuit (pp. 285-297). Springer Netherlands. https://doi.org/10.1007/978-1-4020-8588-8_15