High-level power modeling of CPLDs and FPGAs

L. Shang, Niraj Kumar Jha

Research output: Contribution to conferencePaper

46 Scopus citations

Abstract

In this paper, we present a high-level power modelling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then rise an adaptive regression method to model the FPGA power consumption. Such a high-level model can be used in the inner loop of a system-level synthesis tool to estimate the power consumed by different FPGA resources for different potential system-level synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our high-level power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1% compared to low-level FPGA power simulation methods.

Original languageEnglish (US)
Pages46-51
Number of pages6
StatePublished - Jan 1 2001
EventIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001) - Austin, TX, United States
Duration: Sep 23 2001Sep 26 2001

Other

OtherIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001)
CountryUnited States
CityAustin, TX
Period9/23/019/26/01

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Shang, L., & Jha, N. K. (2001). High-level power modeling of CPLDs and FPGAs. 46-51. Paper presented at IEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001), Austin, TX, United States.