High-level power modeling of CPLDs and FPGAs

L. Shang, N. K. Jha

Research output: Contribution to conferencePaperpeer-review

48 Scopus citations


In this paper, we present a high-level power modelling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then rise an adaptive regression method to model the FPGA power consumption. Such a high-level model can be used in the inner loop of a system-level synthesis tool to estimate the power consumed by different FPGA resources for different potential system-level synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our high-level power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1% compared to low-level FPGA power simulation methods.

Original languageEnglish (US)
Number of pages6
StatePublished - 2001
EventIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001) - Austin, TX, United States
Duration: Sep 23 2001Sep 26 2001


OtherIEEE International Conference on: Computer Design: VLSI in Computers and Processors (ICCD 2001)
Country/TerritoryUnited States
CityAustin, TX

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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