Hierarchical test generation and design for testability of ASPPs and ASIPs

In this paper, we present design for testability (DFT) and hierarchical test generation techniques for facilitating the testing of application-specific programmable processors (ASPPs) and application-specific instruction processors (ASIPs). The method utilizes the register transfer level (RTL) circuit description of an ASPP or ASIP and tries to generate a set of test microcode patterns which can be written into the instruction read-only memory (ROM) of the processor. These lines of microcode dictate a new control/data flow in the circuit and can be used to test modules which are not easily testable. The new control/data flow is used to justify precomputed test sets of a module from the system primary inputs to the module inputs and propagate output responses from the module output to the system primary outputs. If the derived test microcode cannot test all untested modules in the circuit, then test multiplexers are added to the data path to test these modules and thus testability of all modules is guaranteed. This scheme has the advantages of low area and delay overheads (average of 3.1% and 0.4% respectively), high fault coverage (>99.6% for all cases) and at-speed testing. Test generation times are about three orders of magnitude smaller than an efficient gate-level sequential test generator. Only one external test pin is required for the DFT method.