HIERARCHICAL FLOWGRAPH INTEGRATION FOR VLSI ARRAY PROCESSORS.

S. Y. Kung, J. Annevelink, P. Dewilde, S. C. Lo

Research output: Contribution to journalConference articlepeer-review

Abstract

The authors propose a new CAD methodology for highly parallel signal processors. The main issue is how to express parallel algorithms in a notation which is easy to understand by humans and possible to compile into efficient VLSI circuits and/or array processor (systolic/wavefront) machine codes. More specifically, they propose a methodology based on a hierarchical and recursive mapping from algorithms to VLSI array hardwares. In the first phase of the design a powerful signal flow graph (SFG) notation is used to express recurrence and ordering associated with the description of the space-time activities. In the second phase, this description is mapped into a VLSI hardware description or in executable array processor machine codes.

Original languageEnglish (US)
Pages (from-to)288-291
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
StatePublished - Dec 1 1985
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering

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