Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip

L. Lingappan, S. Ravi, A. Raghunathan, N. K. Jha, S. T. Chakradhar

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


In this paper, we present compression techniques for effectively reducing the test data volume requirements of modern systems-on-chip (SoCs). Our techniques are based on the following observations: (i) conventional test compression schemes, which are designed to satisfy various constraints including low hardware overheads and low decompression times, cannot fully exploit compression opportunities present in test data, and (ii) due to the diversity of components used in SoCs (and consequently in their test strategies and test data characteristics), a single compression strategy may not be best suited to handle them. We propose the use of multi-level and heterogeneous test compression schemes to address the above issues, and demonstrate that they can provide significant reductions in test volume above currently known state-of-the-art test compression techniques. We also suggest various architectural customization techniques such as partitioning of decompression functionality between hardware and software, and addition of custom instructions, to improve decompression times and reduce hardware overheads. Experiments with several designs, including an industrial media processing SoC, demonstrate the efficacy of the proposed techniques in achieving test data volume reductions with low overheads.

Original languageEnglish (US)
Pages (from-to)65-70
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
StatePublished - 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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