Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs

Keyphrases

• Low Power 100%
• Hardware Complexity 100%
• Co-synthesis 100%
• Distributed Embedded Systems 100%
• Real-time Distributed 100%
• Partially Reconfigurable FPGA 100%
• Synthesis System 66%
• Scheduler 66%
• Multi-rate 66%
• Real-time Constraints 66%
• System Resources 66%
• Two Dimensional 33%
• Scheduling Algorithm 33%
• Processing Task 33%
• Reconfiguration 33%
• System Optimization 33%
• Evolutionary Algorithms 33%
• Processing Element 33%
• Reconfiguration Overhead 33%
• System Architecture 33%
• Task-oriented 33%
• Priority-based 33%
• Communication Link 33%
• Simultaneous Optimization 33%
• Resource Utilization 33%
• List-based 33%
• Task Engagement 33%
• Schedule Length 33%
• Real-time Reconfiguration 33%
• Multiple Systems 33%
• Cyclic Scheduling 33%
• Resource Reconfiguration 33%
• FPGA Processor 33%
• Dynamically Reconfigurable Devices 33%
• Task Priority 33%
• Algorithm-based 33%
• Scheduled Task 33%

Computer Science

• Field Programmable Gate Array 100%
• Embedded System 100%
• Time Constraint 50%
• Multiobjective 50%
• Reconfiguration 50%
• System Resource 50%
• Experimental Result 25%
• Scheduling Algorithm 25%
• Time Reconfiguration 25%
• Processing Element 25%
• Communication Link 25%
• Resource Utilisation 25%
• Cyclic Scheduling 25%
• Multiple System 25%
• Reconfigurable Device 25%
• Overhead Information 25%
• System Architecture 25%
• Evolutionary Algorithm 25%