Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems

Santhanam Srinivasan, Niraj Kumar Jha

Research output: Contribution to conferencePaperpeer-review

19 Scopus citations


Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems typically have soft or hard performance constraints. The increasing complexity of these systems makes them vulnerable to failures and their use in many safety-critical applications makes fault tolerance an important requirement. This paper is the first to address the problem of automatic hardware-software co-synthesis of fault-tolerant embedded distributed real-time systems in a generalized scenario. We present an algorithm which takes as input the specification of the data-flow information in the form of a task graph, the performance constraints, the fault tolerance requirements and the available hardware resources in the form of processor, ASIC and link libraries. Our algorithm then synthesizes the required hardware as a distributed system in terms of the component processors, ASICs and interconnection links. The tasks are mapped to this hardware such that the overall system cost is minimized while still meeting the performance constraints and the fault tolerance requirements. Our algorithm uses clustering techniques to perform the synthesis. Fault tolerance is added using CRAFT, a technique we recently proposed for CRiticAlity based Fault Tolerance in real-time distributed systems.

Original languageEnglish (US)
Number of pages6
StatePublished - Dec 1 1995
EventProceedings of the 1995 European Design Automation Conference with EURO-VHDL - Brighton, UK
Duration: Sep 18 1995Sep 22 1995


OtherProceedings of the 1995 European Design Automation Conference with EURO-VHDL
CityBrighton, UK

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering


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