Hardware-efficient fair queueing architectures for high-speed networks

Jennifer L. Rexford, Albert G. Greenberg, Flavio G. Bonomi

Research output: Contribution to journalArticlepeer-review

74 Scopus citations


In emerging communication networks, a single link may carry traffic for thousands of connections with different traffic parameters and quality-of-service requirements. High-speed links, coupled with small packet/cell sizes, require efficient switch architectures that can handle cell arrivals and departures every few microseconds, or faster. This paper presents a collection of self-clocked fair queueing (SCFQ) architectures amenable to efficient hardware implementation in network switches. Exact and approximate implementations of SCFQ efficiently handle a moderate range of connection bandwidth parameters, while hierarchical arbitration schemes scale to a large range of throughput requirements. Simulation experiments demonstrate that these architectures divide link bandwidth fairly on a small time scale, preserving connection bandwidth and burstiness properties.

Original languageEnglish (US)
Pages (from-to)638-646
Number of pages9
JournalProceedings - IEEE INFOCOM
StatePublished - Jan 1 1996
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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