TY - GEN
T1 - Hardware-assisted 3D TCAD for predictive capacitance extraction in 32nm SOI SRAMs
AU - Bhoj, A. N.
AU - Joshi, R. V.
AU - Polonsky, S.
AU - Kanj, R.
AU - Saroop, S.
AU - Tan, Y.
AU - Jha, N. K.
PY - 2011
Y1 - 2011
N2 - A comprehensive technology-node/process/layout-independent TCAD flow for guiding FEOL/BEOL analysis/design of 32nm SOI SRAMs is presented using, for the first time, iterative 3D TCAD capacitance extraction assisted by hardware data. The methodology is unique in the industry, giving insight into FEOL/BEOL components independently, when total capacitance is the only experimentally measurable quantity. 32nm SOI simulations from the flow are in excellent agreement with hardware data for two different 6T SRAM macros in the same process. In particular, they isolate the FEOL component, consisting mainly of junction capacitance, as the dominant factor affecting total bitline capacitance variation across wafers, owing to the sensitivity to body doping. Leveraging hardware data, the method is able to effectively predict other key capacitances (e.g., wordline) of generic layouts in the same process, thereby reducing the silicon footprint (cost) for test structures during early phases of technology development.
AB - A comprehensive technology-node/process/layout-independent TCAD flow for guiding FEOL/BEOL analysis/design of 32nm SOI SRAMs is presented using, for the first time, iterative 3D TCAD capacitance extraction assisted by hardware data. The methodology is unique in the industry, giving insight into FEOL/BEOL components independently, when total capacitance is the only experimentally measurable quantity. 32nm SOI simulations from the flow are in excellent agreement with hardware data for two different 6T SRAM macros in the same process. In particular, they isolate the FEOL component, consisting mainly of junction capacitance, as the dominant factor affecting total bitline capacitance variation across wafers, owing to the sensitivity to body doping. Leveraging hardware data, the method is able to effectively predict other key capacitances (e.g., wordline) of generic layouts in the same process, thereby reducing the silicon footprint (cost) for test structures during early phases of technology development.
UR - http://www.scopus.com/inward/record.url?scp=84857007521&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84857007521&partnerID=8YFLogxK
U2 - 10.1109/IEDM.2011.6131673
DO - 10.1109/IEDM.2011.6131673
M3 - Conference contribution
AN - SCOPUS:84857007521
SN - 9781457705052
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 34.7.1-34.7.4
BT - 2011 International Electron Devices Meeting, IEDM 2011
T2 - 2011 IEEE International Electron Devices Meeting, IEDM 2011
Y2 - 5 December 2011 through 7 December 2011
ER -