Guarded evaluation: Pushing power management to logic synthesis/design

Vivek Tiwari, Sharad Malik, Pranav Ashar

Research output: Contribution to conferencePaperpeer-review

61 Scopus citations


The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. This paper describes the development and application of algorithms that use ideas similar to power management, but that are applicable to logic level synthesis/design. The proposed approach is termed guarded evaluation. The main idea here is to determine, on a per clock cycle basis, which parts of a circuit are computing results that will be used, and which are not. The sections that are not needed are then `shut off', thus saving the power used in all the useless transitions in that part of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach. While this paper presents the development of these ideas at the logic level of design - the same ideas have direct application at the register transfer level of design also.

Original languageEnglish (US)
Number of pages6
StatePublished - 1995
EventProceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA
Duration: Apr 23 1995Apr 26 1995


OtherProceedings of the 1995 International Symposium on Low Power Design
CityDana Point, CA, USA

All Science Journal Classification (ASJC) codes

  • General Engineering


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