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Glitch analysis and reduction in register transfer level power optimization
Anand Raghunathan
, Sujit Dey
,
Niraj K. Jha
Electrical and Computer Engineering
Princeton Language and Intelligence (PLI)
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Keyphrases
Circuit Power Consumption
20%
Control Flow
20%
Control Signal
60%
Data Correlation
20%
Data Signal
20%
Glitch
100%
Glitch Reduction
20%
Glitches
100%
Multiplex Networks
20%
Multiplexer
20%
Power Consumption
20%
Power Optimization
100%
Power Saving
20%
Register Transfer Level
100%
Slow Design
20%
Total Power
20%
Computer Science
Control Flow
33%
Control Signal
100%
Data Correlation
33%
Multiplexer
66%
Power Consumption
66%
Power Optimization
100%
Register-Transfer Level
100%
Engineering
Control Flow
33%
Control Signal
100%
Data Path
33%
Data Signal
33%
Electric Power Utilization
66%
Major Portion
33%
Multiplexer
66%
Power Level
100%