Glitch analysis and reduction in register transfer level power optimization

Anand Raghunathan, Sujit Dey, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

We present design-for-Iow-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the control and data path parts of the circuit. Based on the analysis, we develop techniques that attempt to reduce glitching power consumption by minimizing generation and propagation of glitches in the RTL circuit. Our techniques include restructuring multiplexer networks (to enhance data correlations, eliminate glitchy control signals, and reduce glitches on data signals), clocking control signals, and inserting selective rising/falling delays. Our techniques are suited to control-flow intensive designs, where glitches generated at control signals have a significant impact on the circuit's power consumption, and multiplexers and registers often account for a major portion of the total power. Application of the proposed techniques to several examples shows significant power savings, with negligible area and delay overheads.

Original languageEnglish (US)
Title of host publicationLow-Power CMOS Design
PublisherWiley-IEEE Press
Pages568-573
Number of pages6
ISBN (Electronic)9780470545058
ISBN (Print)9780780334298
DOIs
StatePublished - Jan 1 1998

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Computer Science(all)
  • Energy(all)

Fingerprint Dive into the research topics of 'Glitch analysis and reduction in register transfer level power optimization'. Together they form a unique fingerprint.

  • Cite this

    Raghunathan, A., Dey, S., & Jha, N. K. (1998). Glitch analysis and reduction in register transfer level power optimization. In Low-Power CMOS Design (pp. 568-573). Wiley-IEEE Press. https://doi.org/10.1109/9780470545058.sect14