Generation of heterogeneous distributed architectures for memory-intensive applications through high-level synthesis

Keyphrases

• High-level Synthesis 100%
• Memory-intensive Applications 100%
• Distributed Architecture 100%
• Performance Speed 100%
• Application Specific Integrated Circuits 66%
• Array Data 66%
• Power Delay Product 33%
• System Performance 33%
• Performance Improvement 33%
• Synthesis Methods 33%
• Access Latency 33%
• Single chip 33%
• Chip Area 33%
• Memory Architecture 33%
• Distributed Logic 33%
• Data Access 33%
• Partitioning Method 33%
• Benchmark Applications 33%
• Irregular Array 33%
• Min-cut 33%
• Data Access Pattern 33%
• Memory Size 33%
• Balanced Workload 33%
• Memory Organization 33%
• Access Locality 33%
• General-purpose Computing 33%
• Inter-partition Communication 33%
• Architecture-centric 33%
• Integrated Circuit Design 33%
• Memory Design 33%

Computer Science

• High Level Synthesis 100%
• Speed-up 100%
• Distributed Architecture 100%
• Intensive Application 100%
• Application Specific Integrated Circuit 66%
• Performance Improvement 33%
• Systems Performance 33%
• single-chip 33%
• Energy Delay Product 33%
• Bandwidth Requirement 33%
• Synthesis Technique 33%
• Data Access 33%
• Memory Architecture 33%
• Partitioning Technique 33%
• Application Benchmark 33%
• Access Requirement 33%
• Feasible Solution 33%
• Data Access Pattern 33%
• Data Array 33%
• Integrated Circuit Design 33%
• Memory Design 33%