Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Simulation-based testing has been the workhorse of hardware implementation validation. For processors, tandem simulation improves test and debug efficiency by cross-level simulating the Instruction Set Architecture (ISA) and RTL models, and comparing architectural-state variables at the end of each instruction rather than at the end of the whole trace. Further, the simulation may start with the ISA model and switch to the RTL model at some point by transferring the values of the architectural variables, thus speeding up the 'warm-up' phase. However, thus far tandem simulation has been limited to processor designs as other SoC components lack high-level ISA models and thus the notion of instructions. Even for processors, significant manual effort is required in connecting the two models and constructing the necessary controller to synchronize/check/swap between them. This paper leverages the recently proposed Instruction-level Abstractions (ILAs) for generalizing tandem simulation to accelerators. Further, we use the refinement-map that is part of the ILA verification methodology to automate the connection between the ILA and the RTL simulation models for both processors and accelerators. We provide seven case studies to demonstrate the practical applicability of our methodology.

Original languageEnglish (US)
Title of host publicationASP-DAC 2022 - 27th Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages154-159
Number of pages6
ISBN (Electronic)9781665421355
DOIs
StatePublished - 2022
Event27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022 - Virtual, Online, Taiwan, Province of China
Duration: Jan 17 2022Jan 20 2022

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2022-January

Conference

Conference27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022
Country/TerritoryTaiwan, Province of China
CityVirtual, Online
Period1/17/221/20/22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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