TY - GEN
T1 - General-purpose FPGA platform for efficient encryption and hashing
AU - Szefer, Jakub
AU - Chen, Yu Yuan
AU - Lee, Ruby B.
PY - 2010
Y1 - 2010
N2 - Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can be protected by encryption using symmetric-key ciphers, and the integrity of the data can be ensured by using a cryptographic hash function to calculate a "digital fingerprint." In this paper, we propose reconfigurable FPGA hardware components that enable rapid deployment of cryptographic and other algorithms. The novelty of our hardware components is in their general-purpose design which enables easy mappings of algorithms to allow customizations of data protection for different usage scenarios. Since we utilize only a small part of an FPGA chip, our design can be readily integrated with other processing needs of a mobile device, a sensor node or a System-on-Chip. Important block ciphers like the Advanced Encryption Standard (AES) as well as advanced cryptographic hash algorithms like Whirlpool map well onto our general-purpose components. Our solution facilitates easy hardware implementation of customizable encryption and hashing solutions, with area and speed performance comparable to custom FPGA implementations targeted at a specific cipher or hash algorithm. We achieve the best efficiency in Mbps/slice for Whirlpool. Furthermore, the components that we have proposed can be used for many other applications - not just for implementing block ciphers and cryptographic hash functions.
AB - Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can be protected by encryption using symmetric-key ciphers, and the integrity of the data can be ensured by using a cryptographic hash function to calculate a "digital fingerprint." In this paper, we propose reconfigurable FPGA hardware components that enable rapid deployment of cryptographic and other algorithms. The novelty of our hardware components is in their general-purpose design which enables easy mappings of algorithms to allow customizations of data protection for different usage scenarios. Since we utilize only a small part of an FPGA chip, our design can be readily integrated with other processing needs of a mobile device, a sensor node or a System-on-Chip. Important block ciphers like the Advanced Encryption Standard (AES) as well as advanced cryptographic hash algorithms like Whirlpool map well onto our general-purpose components. Our solution facilitates easy hardware implementation of customizable encryption and hashing solutions, with area and speed performance comparable to custom FPGA implementations targeted at a specific cipher or hash algorithm. We achieve the best efficiency in Mbps/slice for Whirlpool. Furthermore, the components that we have proposed can be used for many other applications - not just for implementing block ciphers and cryptographic hash functions.
UR - http://www.scopus.com/inward/record.url?scp=77955887647&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955887647&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2010.5540976
DO - 10.1109/ASAP.2010.5540976
M3 - Conference contribution
AN - SCOPUS:77955887647
SN - 9781424469673
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 309
EP - 312
BT - ASAP 10 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors, Conference Proceedings
T2 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010
Y2 - 7 July 2010 through 9 July 2010
ER -