Gem5-PVT: A framework for FinFET system simulation under PVT variations

FinFET has begun replacing CMOS at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has a higher on-current and lower leakage due to its double-gate structure. A FinFET-based system simulation framework can be very helpful to system architects for early-stage design-space exploration using this new technology. However, such a simulator does not exist. We fill this gap by presenting the details of one such simulation framework, called gem5-PVT, that we have developed. Our simulation framework combines and extends existing lower-level FinFET simulators to support timing, power, and thermal studies of FinFET-based chip multiprocessor systems under process, voltage, and temperature (PVT) variations. It uses a bottom-up modeling approach based on logic/memory cell libraries that have been very accurately characterized using TCAD device simulation. This allows accuracy to bubble up to the system level. The framework is modular and automated, hence enables system designers the flexibility to evaluate various system implementations. It is currently targeted at the 22nm FinFET technology. We report results for two case studies to demonstrate its usefulness. One study shows that more than 62.1× system-level leakage reduction, at the same performance, is possible when using a particular FinFET logic style. Another study characterizes core-to-core frequency and power variations that result from underlying PVT variations and compares the effectiveness of variation-aware scheduling schemes.