GARNET: A detailed on-chip network model inside a full-system simulator

Niket Agarwal, Tushar Krishna, Li Shiuan Peh, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

468 Scopus citations

Abstract

Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing diminishing returns and the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores has become a critical part of the design. Transistor miniaturization has led to high global wire delay, and interconnect power comparable to transistor power. CMP design proposals can no longer ignore the interaction between the memory hierarchy and the interconnection network that connects various elements. This necessitates a detailed and accurate interconnection network model within a full-system evaluation framework. Ignoring the interconnect details might lead to inaccurate results when simulating a CMP architecture. It also becomes important to analyze the impact of interconnection network optimization techniques on full system behavior. In this light, we developed a detailed cycle-accurate interconnection network model (GARNET), inside the GEMS full-system simulation framework. GARNET models a classic ve-stage pipelined router with virtual channel (VC) ow control. Microarchitectural details, such as it-level input buffers, routing logic, allocators and the crossbar switch, are modeled. GARNET, along with GEMS, provides a detailed and accurate memory system timing model. To demonstrate the importance and potential impact of GARNET, we evaluate a shared and private L2 CMP with a realistic state-of-the-art interconnection network against the original GEMS simple network. The objective of the evaluation was to gure out which conguration is better for a particular workload. We show that not modeling the interconnect in detail might lead to an incorrect outcome. We also evaluate Express Virtual Channels (EVCs), an on-chip network ow control proposal, in a full-system fashion. We show that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.

Original languageEnglish (US)
Title of host publicationISPASS 2009 - International Symposium on Performance Analysis of Systems and Software
Pages33-42
Number of pages10
DOIs
StatePublished - 2009
EventInternational Symposium on Performance Analysis of Systems and Software, ISPASS 2009 - Boston, MA, United States
Duration: Apr 26 2009Apr 28 2009

Publication series

NameISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Other

OtherInternational Symposium on Performance Analysis of Systems and Software, ISPASS 2009
CountryUnited States
CityBoston, MA
Period4/26/094/28/09

All Science Journal Classification (ASJC) codes

  • Information Systems
  • Software

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