TY - GEN
T1 - Functional partitioning for low power distributed systems of systems-on-a-chip
AU - Fei, Yunsi
AU - Jha, N. K.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The system level specification is assumed to be given as a set of task graphs. The goal is to partition the task graphs so that each partitioned segment is implemented as an SOC and the embedded system is realized as a distributed system of SOCs. Unlike most previous synthesis and partitioning tools, this technique merges partitioning and system synthesis (allocation, assignment, and scheduling) into one integrated process; both are implemented within a genetic algorithm. Genetic algorithms can escape local minima and explore the partitioning and synthesis design space efficiently. Through integration with an existing SOC synthesis tool, the proposed partitioning technique satisfies both the hard real-time constraints and the SOC area constraint of each partitioned segment. Under these constraints, our tool performs multi-objective optimization. Thus, with a single run of the tool, it produces multiple distributed SOC-based embedded system architectures that trade off the overall distributed system price and power consumption. Experimental results show the efficacy of our technique.
AB - In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The system level specification is assumed to be given as a set of task graphs. The goal is to partition the task graphs so that each partitioned segment is implemented as an SOC and the embedded system is realized as a distributed system of SOCs. Unlike most previous synthesis and partitioning tools, this technique merges partitioning and system synthesis (allocation, assignment, and scheduling) into one integrated process; both are implemented within a genetic algorithm. Genetic algorithms can escape local minima and explore the partitioning and synthesis design space efficiently. Through integration with an existing SOC synthesis tool, the proposed partitioning technique satisfies both the hard real-time constraints and the SOC area constraint of each partitioned segment. Under these constraints, our tool performs multi-objective optimization. Thus, with a single run of the tool, it produces multiple distributed SOC-based embedded system architectures that trade off the overall distributed system price and power consumption. Experimental results show the efficacy of our technique.
UR - http://www.scopus.com/inward/record.url?scp=84962250697&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962250697&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2002.994934
DO - 10.1109/ASPDAC.2002.994934
M3 - Conference contribution
AN - SCOPUS:84962250697
T3 - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
SP - 274
EP - 281
BT - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Y2 - 7 January 2002 through 11 January 2002
ER -