Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

Jinseok Lee; Hossein Valavi; Yinqi Tang; Naveen Verma

Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

Jinseok Lee, Hossein Valavi, Yinqi Tang, Naveen Verma

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multilevel input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm² (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.

Original language	English (US)
Title of host publication	2021 Symposium on VLSI Technology, VLSI Technology 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487802
State	Published - 2021
Event	41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan Duration: Jun 13 2021 → Jun 19 2021

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2021-June
ISSN (Print)	0743-1562

Conference

Conference	41st Symposium on VLSI Technology, VLSI Technology 2021
Country/Territory	Japan
City	Virtual, Online
Period	6/13/21 → 6/19/21

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@inproceedings{299d6eb634f74c57b5f35f965f562c69,

title = "Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs",

abstract = "This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multilevel input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm2 (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.",

author = "Jinseok Lee and Hossein Valavi and Yinqi Tang and Naveen Verma",

note = "Publisher Copyright: {\textcopyright} 2021 JSAP; 41st Symposium on VLSI Technology, VLSI Technology 2021 ; Conference date: 13-06-2021 Through 19-06-2021",

year = "2021",

language = "English (US)",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 Symposium on VLSI Technology, VLSI Technology 2021",

address = "United States",

}

Lee, J, Valavi, H, Tang, Y & Verma, N 2021, Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. in 2021 Symposium on VLSI Technology, VLSI Technology 2021. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 41st Symposium on VLSI Technology, VLSI Technology 2021, Virtual, Online, Japan, 6/13/21.

Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. / Lee, Jinseok; Valavi, Hossein; Tang, Yinqi et al.
2021 Symposium on VLSI Technology, VLSI Technology 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

AU - Lee, Jinseok

AU - Valavi, Hossein

AU - Tang, Yinqi

AU - Verma, Naveen

PY - 2021

Y1 - 2021

N2 - This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multilevel input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm2 (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.

AB - This paper presents an in-memory computing (IMC) macro in 28nm for fully row/column-parallel matrix-vector multiplication (MVM), exploiting precise capacitor-based analog computation to extend from binary input-vector elements to 5-b input-vector elements, for 16x increase in energy efficiency and 5x increase in throughput. The 1152(row)x256(col.) macro employs multilevel input drivers based on a digital-switch DAC implementation, which preserve compute accuracy well beyond the 8-b resolution of the output ADCs, and whose area is halved via a dynamic-range doubling (DRD) technique. The macro achieves the highest reported IMC energy efficiency of 5796 TOPS/W and compute density of 12 TOPS/mm2 (both normalized to 1-b ops). CIFAR-10 image classification is demonstrated with accuracy of 91%, equal to the level of ideal SW implementation.

UR - http://www.scopus.com/inward/record.url?scp=85125507908&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85125507908&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:85125507908

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2021 Symposium on VLSI Technology, VLSI Technology 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 41st Symposium on VLSI Technology, VLSI Technology 2021

Y2 - 13 June 2021 through 19 June 2021

ER -

Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

Abstract

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Conference

All Science Journal Classification (ASJC) codes

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