Full-system chip multiprocessor power evaluations using FPGA-based emulation

Abhishek Bhattacharjee, Gilberto Contreras, Margaret Rose Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Scopus citations

Abstract

The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS, Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35 X speedup compared to full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.

Original languageEnglish (US)
Title of host publicationISLPED'08
Subtitle of host publicationProceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages335-340
Number of pages6
DOIs
StatePublished - Dec 17 2008
EventISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
Duration: Aug 11 2008Aug 13 2008

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryIndia
CityBangalore
Period8/11/088/13/08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Keywords

  • Design
  • Measurement
  • Performance

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