Quantum computation can solve certain problems much faster than classical computation. However, quantum computations are more susceptible to errors than conventional digital computations. Thus, a fault-tolerant (FT) quantum circuit design is required for a practical implementation. Quantum circuits consist of a cascade of quantum gates. These gates are themselves realized using primitive quantum operations that are supported by the quantum physical machine description (PMD). As different quantum systems are associated with different Hamiltonians, they have different PMDs. In addition, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for the set of primitive quantum operations supported by the given PMD. In this paper, an FT quantum logic synthesis (FTQLS) methodology and tool is described for six different PMDs. A methodology, such as this, which can be targeted at multiple PMDs, has not been attempted before, to the best of our knowledge. The input to FTQLS is an unoptimized quantum circuit realized using a set of commonly used gates and its output is an optimized FT quantum circuit that only comprises of primitive quantum operations supported by the given PMD. FTQLS does technology mapping for different PMDs and then converts non-FT circuits to FT circuits. For technology mapping, it utilizes an optimized quantum gate library targeted at various PMDs that decomposes gates into primitive operations. Efficient conversion to FT circuits is done by integrating two quantum compilers and an FT cache table into FTQLS. For improving the synthesis results, an FT set of gates that is directly supported by each PMD is proposed. Quantum circuit optimization is done by utilizing quantum identity rules. The performance of FTQLS is evaluated using two cost metrics: number of primitive operations (#ops) and execution cycles on the critical path (#cycles). Experiment results show that the decrease in #ops varies between 58.1% and 87.0% and in #cycles between 42.8% and 76.4%, on an average, depending on the PMD.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jun 2014|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Fault-tolerant circuit
- physical machine description
- quantum compilation
- quantum computing
- quantum logic synthesis.