TY - GEN
T1 - fMAXExceeding 3 GHz in Self-Aligned Zinc-Oxide Thin-Film Transistors with Micron-Scale Gate Length
AU - Ma, Yue
AU - Wagner, Sigurd
AU - Verma, Naveen
AU - Sturm, James C.
N1 - Funding Information:
Large-area electronic (LAE) metal-oxide thin-film transistors (TFTs) with and/or beyond 1 GHz demonstrated over recent years [1-3] enable critical circuits and systems towards wireless applications in Internet of Things and 5G/6G (e.g., a 1-GHz phased array for far-field radiation beam steering [4]). Since most existing approaches towards GHz TFTs rely on improved charge-carrier mobility through high-temperature deposition of semiconductors and/or submicron TFT feature size achieved by electron-beam lithography, they are incompatible with low-cost, large-area, and flex-substrate fabrication of TFTs. By additional dependence on gate resistance , opens broader device engineering space to maintain large-area and flex-compatibility, and motivates -limited circuit/system topologies [4]. Here, we show that with optimal TFT bias voltages and reduced through TFT width scaling, a record-high exceeding 3 GHz is achieved in self-aligned zinc-oxide (ZnO) TFTs with gate length of ~1?, patterned by photolithography, with a maximum process temperature of ~200?℃. A high-frequency non-quasi-static TFT model [5] is used to guide the device engineering efforts towards this result. Device Fabrication Fig. 1(a) shows the cross-section of the bottom-gate staggered ZnO TFT [5]. Its key features include: (1) a composite gate electrode of 10-nm Cr/110-nm Al/40-nm Cr to reduce ; (2) photolithography-only patterning (no electron-beam lithography) for minimum gate length of ~1?; (3) self-aligned source/drain metal patterning, resulting in length of source/drain-to-gate overlaps ~0.5?. Device Characterization Results and Analysis Fig. 1 shows typical transfer and output curves of ZnO TFTs, and their DC metrics. Fig. 2 shows the high-frequency TFT model and equations for TFT parameter extraction. With the TFT characterized as a two-port network, values for TFT parameters (i.e., , , , , , , and ) can be extracted from the measured Y-parameters [5]. , , , and are mostly determined by TFT layout and geometry, and thus they are nearly independent of bias voltages. On the other hand, the strongly voltage-dependent and require identifying the optimal bias voltages for maximum . Figs. 3(a) and 3(b) show the extracted and for ⁄ = 50?⁄~1?. The competing effects of (high desired) and (low desired) on lead to optimal bias voltages of = = 6? in Fig. 3(c), which maximize in the saturation region, below the thermally-induced breakdown limit [5]. Beyond the optimization of TFT bias voltages, can be further improved by reducing through TFT width scaling, since is the major resistive loss within TFTs. Figs. 4(a) and 4(b) show the maximum available power gain and stability factor for a range of channel widths , measured at = = 6?. Fig. 4(c) shows that an exceeding 3 GHz is observed in the = 15? TFT. As compared to TFTs with larger , the = 15? TFT shows slightly worse and in Fig. 5(a), due to lower current and thus smaller ∙ power, as less heating lowers the effective electron mobility [6]. While this reduces the of the = 15? TFT at low frequencies in Fig. 4(a), the reduced and thus < 1 maintained up to 3 GHz lead to beyond 3 GHz. Finally, the TFT parameters extracted from the width scaling experiment (the value for is estimated from the sheet resistance and geometry of the gate electrode), summarized in Fig. 5(b), are used to simulate and for the = 15? TFT. Figs. 5(c) and 5(d) show that the simulated and closely match measurements up to 3 GHz, validating the device characterization and the high-frequency modeling. Conclusions Through the optimization of bias voltages and the reduction of resistive loss within TFTs achieved by width scaling, this work demonstrates self-aligned ZnO TFTs with exceeding 3 GHz, which is among the highest for metal-oxide TFTs with large-area and flex-compatibility. These results suggest that, even with limited channel mobility and using photolithography, TFT parameter engineering is a promising path to GHz LAE systems with -limited operation. Therefore, robust GHz modeling methodology will be essential to consolidate the understanding of TFT operation, and to guide future device optimization (e.g., to further reduce for higher ). This work was supported by the Center for Brain-Inspired Computing, one of six centers in JUMP sponsored by DARPA, and the Princeton Program in Plasma Science and Technology. The Princeton PMI cleanroom facilities were used for this project. [1] C. Tückmantel et al., IEEE-EDL, vol. 41, p. 1786, (2020). [2] Y. Mehlman et al., 75th DRC, p. 1, (2017). [3] S. Li et al., IEDM Tech. Dig., p. 40.5.1, (2020). [4] C. Wu et al., Nat. Electron., vol. 4, p. 757, (2021). [5] Y. Ma et al., IEEE OJ-SSCS, vol. 2, p. 177, (2022). [6] F. Torricelli et al., IEEE-TED, vol. 58, p. 2610, (2011).
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Large-area electronic (LAE) metal-oxide thin-film transistors (TFTs) with f{T} and/or f{MAX} beyond 1 GHz demonstrated over recent years [1]-[3] enable critical circuits and systems towards wireless applications in Internet of Things and 5G/6G (e.g., a 1-GHz phased array for far-field radiation beam steering [4]). Since most existing approaches towards GHz TFTs rely on improved charge-carrier mobility through high-temperature deposition of semiconductors and/or submicron TFT feature size achieved by electron-beam lithography, they are incompatible with low-cost, large-area, and flex-substrate fabrication of TFTs. By additional dependence on gate resistance R{G}, f{MAX} opens broader device engineering space to maintain large-area and flex-compatibility, and motivates f{MAX}-limited circuit/system topologies [4]. Here, we show that with optimal TFT bias voltages and reduced R{G} through TFT width scaling, a record-high f{MAX} exceeding 3 GHz is achieved in self-aligned zinc-oxide (ZnO) TFTs with gate length of \sim 1\ \mu m, patterned by photolithography, with a maximum process temperature of ∼200 °C. A high-frequency non-quasi-static TFT model [5] is used to guide the device engineering efforts towards this result.
AB - Large-area electronic (LAE) metal-oxide thin-film transistors (TFTs) with f{T} and/or f{MAX} beyond 1 GHz demonstrated over recent years [1]-[3] enable critical circuits and systems towards wireless applications in Internet of Things and 5G/6G (e.g., a 1-GHz phased array for far-field radiation beam steering [4]). Since most existing approaches towards GHz TFTs rely on improved charge-carrier mobility through high-temperature deposition of semiconductors and/or submicron TFT feature size achieved by electron-beam lithography, they are incompatible with low-cost, large-area, and flex-substrate fabrication of TFTs. By additional dependence on gate resistance R{G}, f{MAX} opens broader device engineering space to maintain large-area and flex-compatibility, and motivates f{MAX}-limited circuit/system topologies [4]. Here, we show that with optimal TFT bias voltages and reduced R{G} through TFT width scaling, a record-high f{MAX} exceeding 3 GHz is achieved in self-aligned zinc-oxide (ZnO) TFTs with gate length of \sim 1\ \mu m, patterned by photolithography, with a maximum process temperature of ∼200 °C. A high-frequency non-quasi-static TFT model [5] is used to guide the device engineering efforts towards this result.
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U2 - 10.1109/DRC58590.2023.10186903
DO - 10.1109/DRC58590.2023.10186903
M3 - Conference contribution
AN - SCOPUS:85167869678
T3 - Device Research Conference - Conference Digest, DRC
BT - 2023 Device Research Conference, DRC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 Device Research Conference, DRC 2023
Y2 - 25 June 2023 through 28 June 2023
ER -