Chip multiprocessors are of increasing importance due to recent difficulties in achieving higher clock frequencies in uniprocessors, but their success depends on finding useful work for the processor cores. This paper addresses this challenge by presenting a simple compiler approach that extracts non-speculative thread-level parallelism from sequential codes. We present initial results from this technique targeting a validated dual-core processor model, achieving speedups ranging from 948% with an average of 25% for important benchmark loops over their single-threaded versions. We also identify important next steps found during our, pursuit of higher degrees of automatic threading.
|Original language||English (US)|
|Number of pages||4|
|Journal||IEEE Computer Architecture Letters|
|State||Published - Jan 1 2006|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture