Abstract
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involves converting program control flow into conditional, or predicated, instructions. This process is known as if-conversion. In order to effectively apply if-conversion, one must address two major issues: what should be if-converted and when the if-conversion should be applied. A compiler's use of predication as a representation is most effective when large amounts of code are if-converted and if-conversion is performed early in the compilation procedure. On the other hand, the final code generated for a processor with predicated execution requires a delicate balance between control flow and predication to achieve efficient execution. The appropriate balance is tightly coupled with scheduling decisions and detailed processor characteristics. This paper presents an effective compilation framework that allows the compiler to maximize the benefits of predication as a compiler representation while delaying the final balancing of control flow and predication to schedule time.
Original language | English (US) |
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Title of host publication | Proceedings of the Annual International Symposium on Microarchitecture |
Publisher | IEEE Comp Soc |
Pages | 92-103 |
Number of pages | 12 |
ISBN (Print) | 0818679778 |
DOIs | |
State | Published - 1997 |
Externally published | Yes |
Event | Proceedings of the 1997 30th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-30 - Triangle Park, NC, USA Duration: Dec 1 1997 → Dec 3 1997 |
Other
Other | Proceedings of the 1997 30th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-30 |
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City | Triangle Park, NC, USA |
Period | 12/1/97 → 12/3/97 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Software