Formal control techniques for power-performance management

Qiang Wu; Philo Juang; Margaret Martonosi; Li Shiuan Peh; Douglas W. Clark

doi:10.1109/MM.2005.87

Formal control techniques for power-performance management

Qiang Wu, Philo Juang, Margaret Martonosi, Li Shiuan Peh, Douglas W. Clark

Research output: Contribution to journal › Article › peer-review

85 Scopus citations

Abstract

These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.

Original language	English (US)
Pages (from-to)	52-62
Number of pages	11
Journal	IEEE Micro
Volume	25
Issue number	5
DOIs	https://doi.org/10.1109/MM.2005.87
State	Published - Sep 2005

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2005.87

Cite this

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title = "Formal control techniques for power-performance management",

abstract = "These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.",

author = "Qiang Wu and Philo Juang and Margaret Martonosi and Peh, {Li Shiuan} and Clark, {Douglas W.}",

note = "Funding Information: This research was supported by NSF grants CCR-0086031 (ITR) and CNS-0410937. Martonosi{\textquoteright}s work is also supported in part by Intel, IBM, and SRC.",

year = "2005",

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T1 - Formal control techniques for power-performance management

AU - Wu, Qiang

AU - Juang, Philo

AU - Martonosi, Margaret

AU - Peh, Li Shiuan

AU - Clark, Douglas W.

N1 - Funding Information: This research was supported by NSF grants CCR-0086031 (ITR) and CNS-0410937. Martonosi’s work is also supported in part by Intel, IBM, and SRC.

PY - 2005/9

Y1 - 2005/9

N2 - These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.

AB - These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.

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DO - 10.1109/MM.2005.87

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VL - 25

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JO - IEEE Micro

JF - IEEE Micro

IS - 5

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Formal control techniques for power-performance management

Abstract

All Science Journal Classification (ASJC) codes

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