FinPrin: FinFET logic circuit analysis and optimization under PVT variations

Keyphrases

• Temperature Variation 100%
• Process Variation 100%
• Fin Field-effect Transistor (FinFET) 100%
• Logic Circuit 100%
• Circuit Optimization 100%
• Processing Temperature 100%
• Voltage Variation 100%
• Circuit Analysis 100%
• Static Timing Analysis 80%
• Circuit Level 40%
• Algorithm Analysis 40%
• Leakage Power 40%
• FinFET Circuits 40%
• Power Distribution 40%
• Dynamic Power 40%
• Timing Model 40%
• Monte Carlo Simulation 20%
• Computational Complexity 20%
• Gate Delay 20%
• Logic Gates 20%
• Device Simulation 20%
• Power Analysis 20%
• Macromodel 20%
• Circuit Delay 20%
• Bulk CMOS 20%
• Operating Temperature 20%
• Logic Library 20%
• Short Channel Effects 20%
• 22 Nm Node 20%
• Deterministic Optimization 20%
• Average Absolute Error 20%
• Output Gate 20%
• Convergence Issues 20%
• Silicon-on-insulator FinFET 20%
• Quasi-Monte Carlo Simulation 20%
• Output Slope 20%
• Leakage Distribution 20%

Engineering

• Electric Network Analysis 100%
• Logic Circuit 100%
• Power Distribution 100%
• Nodes 50%
• Macromodel 50%
• Delay Circuits 50%
• Computational Complexity 50%
• Silicon on Insulator 50%
• Optimization Method 50%
• Operating Temperature 50%
• And Logic Gate 50%
• Average Absolute Error 50%
• Process Variation 50%

Computer Science

• Timing Analysis 100%
• Monte Carlo Simulation 50%
• Dynamic Power 50%
• Computational Complexity 25%
• Process Variation 25%
• Logic Gate 25%
• And Gate 25%
• Power Analysis 25%