FinPrin: FinFET logic circuit analysis and optimization under PVT variations

Computer Science

• Timing Analysis 100%
• Monte Carlo Simulation 50%
• Power Distribution 50%
• Dynamic Power 50%
• Computational Complexity 25%
• Process Variation 25%
• Logic Gate 25%
• And Gate 25%
• Power Analysis 25%

Keyphrases

• Average Absolute Error 20%
• Output Gate 20%
• Convergence Issues 20%

Engineering

• Average Absolute Error 50%