FinPrin: Analysis and optimization of FinFET logic circuits under PVT variations

Keyphrases

• Algorithm Analysis 20%
• Average Absolute Error 20%
• Bulk CMOS 20%
• Dynamic Power 40%
• Fin Field-effect Transistor (FinFET) 100%
• Gate Delay 20%
• Leakage Power 40%
• Logic Circuit 100%
• Logic Gates 20%
• Monte Carlo Simulation 20%
• Operating Temperature 20%
• Output Curve 20%
• Output Gate 20%
• Power Analysis 20%
• Process Variation 100%
• Processing Temperature 100%
• Promising Solutions 20%
• Quasi-Monte Carlo Simulation 20%
• Static Timing Analysis 60%
• Technology Node 20%
• Temperature Variation 100%
• Timing Model 20%
• Voltage Variation 100%

Computer Science

• And Gate 33%
• Dynamic Power 66%
• Logic Gate 33%
• Monte Carlo Simulation 66%
• Power Analysis 33%
• Process Variation 33%
• Relative Performance 33%
• Timing Analysis 100%

Engineering

• And Logic Gate 33%
• Average Absolute Error 33%
• Logic Circuit 100%
• Nodes 33%
• Operating Temperature 33%
• Process Variation 33%
• Relative Performance 33%