FinPrin: Analysis and optimization of FinFET logic circuits under PVT variations

Continued scaling of bulk CMOS technology is facing formidable challenges. As an alternative, FinFETs offer a promising solution for the 22nm technology node and beyond though they still suffer from process, voltage, and temperature (PVT) variations. Thus, in order to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis (STA). In this paper, we consider voltage and temperature variations in addition to process variations. We propose a simplified FinFET timing model with an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared to accurate quasi Monte-Carlo (QMC) simulations. We extend an existing SSTA algorithm to statistical leakage and dynamic power analysis as well, and evaluate its performance relative to Monte-Carlo (MC) simulation. Finally, we show that FinFET logic circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.