FinPrin: Analysis and optimization of FinFET logic circuits under PVT variations

Yang Yang, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Continued scaling of bulk CMOS technology is facing formidable challenges. As an alternative, FinFETs offer a promising solution for the 22nm technology node and beyond though they still suffer from process, voltage, and temperature (PVT) variations. Thus, in order to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis (STA). In this paper, we consider voltage and temperature variations in addition to process variations. We propose a simplified FinFET timing model with an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared to accurate quasi Monte-Carlo (QMC) simulations. We extend an existing SSTA algorithm to statistical leakage and dynamic power analysis as well, and evaluate its performance relative to Monte-Carlo (MC) simulation. Finally, we show that FinFET logic circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

Original languageEnglish (US)
Title of host publicationProceedings - 26th International Conference on VLSI Design, VLSID 2013 - Concurrently with 12th International Conference on Embedded Systems Design, ES 2013
Pages350-355
Number of pages6
DOIs
StatePublished - Apr 4 2013
Event2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013 - Pune, India
Duration: Jan 5 2013Jan 10 2013

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other2013 26th International Conference on VLSI Design, VLSID 2013 and 12th International Conference on Embedded Systems, ES 2013
CountryIndia
CityPune
Period1/5/131/10/13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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